Lines Matching refs:bit
28 andl $0xFFFFFFF8,%esp / align following 64bit arg
29 subl $0x8,%esp / 64bit nRegReturn
30 pushl %ecx / 32bit pCallStack
31 pushl %edx / 32bit nVtableOffset
32 pushl %eax / 32bit nFunctionIndex
34 movl 12(%esp),%eax / 64 bit nRegReturn, lower half
46 andl $0xFFFFFFF8,%esp / align following 64bit arg
47 subl $0x8,%esp / 64bit nRegReturn
48 pushl %ecx / 32bit pCallStack
49 pushl %edx / 32bit nVtableOffset
50 pushl %eax / 32bit nFunctionIndex
63 andl $0xFFFFFFF8,%esp / align following 64bit arg
64 subl $0x8,%esp / 64bit nRegReturn
65 pushl %ecx / 32bit pCallStack
66 pushl %edx / 32bit nVtableOffset
67 pushl %eax / 32bit nFunctionIndex
69 movl 12(%esp),%eax / 64 bit nRegReturn, lower half
70 movl 16(%esp),%edx / 64 bit nRegReturn, upper half
82 andl $0xFFFFFFF8,%esp / align following 64bit arg
83 subl $0x8,%esp / 64bit nRegReturn
84 pushl %ecx / 32bit pCallStack
85 pushl %edx / 32bit nVtableOffset
86 pushl %eax / 32bit nFunctionIndex
88 flds 12(%esp) / 64 bit nRegReturn, lower half
100 andl $0xFFFFFFF8,%esp / align following 64bit arg
101 subl $0x8,%esp / 64bit nRegReturn
102 pushl %ecx / 32bit pCallStack
103 pushl %edx / 32bit nVtableOffset
104 pushl %eax / 32bit nFunctionIndex
106 fldl 12(%esp) / 64 bit nRegReturn
118 andl $0xFFFFFFF8,%esp / align following 64bit arg
119 subl $0x8,%esp / 64bit nRegReturn
120 pushl %ecx / 32bit pCallStack
121 pushl %edx / 32bit nVtableOffset
122 pushl %eax / 32bit nFunctionIndex
124 movl 12(%esp),%eax / 64 bit nRegReturn, lower half